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v e c t r on i n t e r na t io n a l 1 6 6 g l o v e r a v e nue , n or w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e- m a i l: v e ct r o n @ v e c t ro n . c o m w h a t s i n s i d e ? w h a t d o e s i t d o ? p a g e s 3 - 5 h o w i s i t b u i l t ? p a g e s 6 - 11 h o w d o e s i t p e r f o rm ? p a g e s 1 2 - 1 4 f e a t u re s : pll with quartz stabilized vcxo output jitter less than 20 ps loss of signal (los) ala r m return to nominal clock upon los input data rates from 8 kb/s to 65 mb/s surface mount option t ri-state output user defined pll loop response nrz data compatible robust hermetic ceramic package single o r +5. 0 v suppl y (+3.3 v option available) b e n e f i t s : flexible modular solution reduce design time increase circuit reliability less board space reduces component count 1 o f 17 what is the main benefit of the tru-050? it? a single drop-in quartz stabilized pll solution. h o w i s i t u s e d ? p a g e s 1 5 - 1 8 h o w i s i t p a c k a g e d ? h o w i s i t o r d e re d ? p a g e 19 v ectron international's tru-050 module is a user-configured, phase-locked loop (pll) solution designed to simplify a wide variety of clock recovery and data retiming, frequency translation and clock smoothing applications. the device features a phase-lock loop asic with a quartz stabilized vcxo for superior stability and jitter performance. thi s h igh l y i n t e grate d m o d u l e pro v ide s u nsurp a ssed pe r f o r m ance , rel i ab i l i t y a n d qualit y . t h e p r o p r i e t a r y asi c dev i c e i n clude s a r e f i n e d p h ase detec t o r , a loo p f i lte r o p -amp, a loss of signal alarm with clock return to nominal feature, a vcxo circuit, and an optional 2 n divided output. the asic and quartz resonator are housed in a hermetic 16-pin dil ceramic package with optional thru-hole or surface mount leads. the vcxo frequency (out1) and division factor (out2) are factory set in accordance with customer specifications. pll response is optimized for each application by the selection of three external passive components. software is available from vectron to aid in loop filter component selection and loop response modeling. w h a t d o e s i t d o?
v e c t r o n i n t e r n a t i on a l 1 6 6 glo v e r a v e n u e , n o r w a l k , c t 0 6 85 6 - 5 160 t e l : 1 -88 - v e c t r o n - 1 e - ma i l: v e ct r o n @ v e c t ro n . c o m input nrz data rates input rz data and clock rates 1 nominal output frequency output 1 output 2 2 supply voltage 3 supply cu r r ent (v dd = 5.5 v) output voltage levels (v dd = 4.5 v) output logic high 4 output logic low 4 t ransition times: 4 rise time (0.5 v to 2.5 v) fall time (2.5 v to 0.5 v) symmetry or duty cycle 5 output 1 output 2 recovered clock input data input logic high input logic low control voltage bandwith (-3 db,vc = 2.50 v) sensitivity @ vc = vo loss of signal indication 6 output logic high output logic low nominal output frequency on loss of signal: 7 output 1 output 2 phase detector gain d a t ain d a t ain out1 out2 v dd i dd v oh v ol t r t f sym 1 sym 2 r clk v ih v il bw d f/ d v c l os v oh v ol out1 out2 k d 0.008 0.008 12.0 0.05 4.5 25 2.5 - 0.5 0.5 40 45 40 2.0 - 50 2.5 - -75 ppm -75 ppm 65.536 32.768 65.536 32.768 5.5 63 - 0.5 5 5 60 55 60 - 0.8 - - 0.5 75 ppm 75 ppm mhz mhz mhz mhz v ma v v ns ns % % % v v khz ppm/v v v ppm from fo 1 ppm from fo 2 v/rad 1 . for input rz data, manchester encoded data, and input clock recovery applications, the output clock must run at two times the input rate to ensure that the input is clocked correctly. since the output clock has a max- imum frequency of 65.536 mhz, these inputs are limited to a maximum rate of 32.768 mhz. 2 . out2 is a binary submultiple of out1, or it may be disabled. 3 . a 3.3 volt supply option is also available. 4 . figure 1 defines these parameters. figure 2 illustrates the equivalent five-gate mttl load and operating conditions under which these parameters are specified and tested. 5 . symmetry is the on time/period in percent with v s = 1.4 v for ttl, per figure 1. 6 . a loss of signal (los) indicator is set to a logic high if no transitions are detected at d a t ain after 256 clock cycles. as soon as a transition occurs at d a t ain, los is set to a logic lo w . 7 . a c c u r a c y at r o o m t e m pe r at ur e. s t a bi l i t y over temperature is typicall y + 20 ppm. parameter symbol min max unit see figure 1 1 . -0.53 x data density t able 1. figure 1. figure 2. 2 o f 1 7
v e c t r o n i n t e r na t io n al 1 6 6 g l o v e r a v e nue , n o r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e- m a i l : v e ct r o n @ v e c t ro n . c o m pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 symbol v c opn opout opp losin pho da t ain gnd clkin los rclk rd a t a out2 hiz out1 v cc function control voltage input to internal voltage controlled crystal oscillator (vcxo). negative input terminal to internal operational amplifie r . output terminal of internal operational amplifie r . positive input terminal to internal operational amplifie r . w ith losin set to a logic high, the external input to the vcxo (vc) is disabled and the vcx o returns to it? nominal center frequency. with losin set to logic low, the external input to the vcxo is enabled. the losin input has an internal pull-down resisto r . output signal produced by phase detecto r . input data stream to phase detector (tll switching thresholds). circuit and cover ground. input clock signal to phase detector (ttl switching thresholds). loss of signal indicator is set to a logic high if no transitions a r e detected at d a t ain after 256 clock cycles. as soon as a transition occurs at da t ain, los is set to a logic low . ttl compatible recovered clock. ttl compatible recovered data stream. divided version of internal vcxo output clock (ttl). when set to a logic low, output pins out1, out2, rclk, and rd a t a buffers are set to high-impedance state. when set to a logic high or no connect, the device functions and output pins out1, out2, rclk, and rd a t a are active. this input has an internal pull-up resisto r . output clock of internal vcxo (ttl). +5.0 v ?0% supply voltage (+3.3 v option available). t able 2. figure 3. t o p v i e w 3 o f 1 7 why would someone buy a tru-050? t o save design time, reduce component count, conserve b o a r d s p a c e , and optimize manufacturing efficienc y .
v e c t r o n i n t e r n a t i o n a l 1 6 6 g l ove r a v enue , no r w a l k, c t 0685 6- 5 16 0 t e l : 1 - 8 8 - v e c t r o n - 1 e -m a i l: v e c t r o n @ v e c t ro n . c o m p h a s e d e t e c t o r t h e p h as e d et e c t or i s d es i g n e d t o a c ce p t a n n r z d a ta s trea m a t d a t a i n ( p i n 7 - r ef e r t o f i gu r e 5 ) , bu t m a y b e u sed f o r c l o c k s i g n a l s a n d o t h e r d a t a t y p e s . the i n p u t b u f f ers a re d e s i g ne d t o s w i t c h a t a t t l s w i t c h i n g t h r e s h o l d o f 1. 4 v . the phase detector? inputs are: ?da t ain (pin 7) - the input clock or nrz data signal ?clkin (pin 9) - the clock signal feedback from the vcxo output out1 or out2 and the outputs are: ?rclk (pin 11) - the regenerated clock signal ?rd a t a (pin 12) - the retimed data signal ?pho (pin 6) - the phase detector output ?los (pin 10) - a loss of signal detector the phase relationship between the regenerated clock signal, rclk (pin 11), and the regenerated data signal, rd a t a (pin 12), is shown in figure 6. figure 4. 4 o f 17 th e tru-05 0 is a user-configured phase-locked loop (pll) integrated circuit. it includes a voltage controlled crystal oscillator (vcxo), an operational amplifier, a phase detector, and additional integrated functions for use in digital synchronization applications. these applications include timing recovery and data pulse restoration for data signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis. h o w i s i t b u i l t ? t r u - 0 5 0 e l e m e n t s what is the output of the phase detector? t he t r u - 05 0 p h a s e d e t ec to r o ut p ut is a dc signal, under locked conditions, and i s n o m i n a l l y 2 . 5 v o l t s . t h e ph a s e e r ror ( w h i c h is typically a pulse for digital phase detectors) is converted to a dc level, making it easy to design the loop filte r . how long does the tru-050 take to detect a loss of signal? if there are no transitions on d a t ain for a period of 256 clock cycles, los is set to a logic 1. los is reset to logic 0 as soon as there are d a t ain transitions.
v e c t r o n i n t e r n a t i o n al 1 6 6 g l o v e r a v e n ue , no r w a l k , c t 0685 6- 5 16 0 t e l : 1 - 8 8 - v e c t r o n - 1 e -m a i l: v ec t r o n @ v e c t ro n . c o m the falling edge of rclk is coincident with the center of the regenerated nrz rd a t a pulse. figure 6 shows a 1010 data stream with a 100% data transition density. in general, this will not be the case and input d a t a w i ll h a v e f ew er d a t a t ra n s i t i o n s . however, the phase detector will still seek to align the falling edge of the rclk signal with the center of each rd a t a pulse. for applications where the input clock or data signal, d a t ain, is very low in frequency (<200khz), clock information may pass through the phase detector because of its finite low pass characteristic. in applications such as this, an additional pole may be necessary in the loop filter to attenuate these ac components prior to the vcxo input. please contact vectron? applications engineering staff for further detail. figure 5. figure 7. figure 6. figure 8. 5 o f 17 how is it manufactured? the tru-050 is assembled in ?tate of the art clas s 1 00 and class 10,000 clean r ooms using leading edge, high volume automation equip- ment and advanced asic technolog y . p h a s e d e t e c t o r g a i n c a l c u l a t i o n the schematic diagram (figure 7) shows a simplified representation of the phase detector's basic e r ror generation function. the actual circuit is more complex and includes circuitry to reduce the tru-050 's dependence on input data duty-cycle. in general, th e tru-05 0 is insensitive to duty cycle and duty cycle changes. this circuit provides a output (v d ) dc level which is proportional to the relative phase of d a t ain (pin 7) and clkin (pin 9). a plot of the output (v d ) versus relative phase is shown in figur e 8. the slope of the output (v d ) versus relative phase (0 e ) is 5v/ 2 p . the phase detector block also includes an output gain stage which should be considered when calculating the gain of the complete phase detector block. this gain stage has a gain of 2/3, and converts the differential signal to a single-ended dc output.
l o s a n d l o s i n the los circuit provides an output alarm flag when the d a t ain input signal is lost. the los output is set ?ogic high?after 256 consecutive clkin periods with no d a t ain transitions. this signal can then be used to either flag external alarm circuits and/or drive th e tru-050 s losin circuit. when the losin input is set ?ogic high,?the loop filter op-amp output is set mid supply to facilitate fast lockup when d a t ain is restored. in addition, the vcxo control voltage is internally set to hold the vcxo at its nominal frequency (?5 ppm). when losin is low or has no connection, the vcxo? control voltage input is enabled (losin has an internal pull-down resistor). l o o p f i l t e r although various loop filter configurations may be considered, mos t tru-05 0 applications use the basic integrator filter of figure 10. this type of filter provides high dc gain to ensure proper clock and data alignment. the ratio of r1 to rf sets midband gain and can be used to adjust the loop bandwidth. the time constant, set by rf and cf, should be selected to be about one decade below the open loop bandwidth to provide good phase margin. t h e r e f e r e n c e f o r t h e n o n - i n v e r t i n g i n p u t i s s e t a t m i d s u p p l y b y r 2 a n d r 3 . software is available to help in the selection of r1, cf and r f . v e c t r on i n t e r n a t ion a l 1 6 6 g l o v e r a v e n u e , n or w a l k , c t 06 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e- m a i l: v e ct r o n @ v e c t ro n . c o m phase detector gain = [5v/2 p ] * [2/3] * d = 0.53 * d where d = input data transition density. for example d = 1 for 100% transition density (e.g., clock signal) and d = 0.5 for 50% transition density (e.g., balanced nrz data). figure 9. figure 10. 6 o f 1 7
v c x o the tru-050 's vcxo is a varactor-tuned crystal oscillator which produces an output frequency controlled by a control voltage, v c . the tracking range of the vcxo is specified as absolute pull range (apr) when ordered. an apr of ?0 ppm guarantees that th e tru-05 0 can track an input source frequency with ?0 ppm stability over all operating conditions, including temperature, time, power supply and load variations. the value of v c is varied between 0.5 v to 4.5 v to achieve the specified apr. a typical frequency versus v c curve for the vcxo in th e tru-05 0 is shown in figure 11. when designing plls, the vcxo gain (kv in hz/v or rad/vs) is an important parameter. as a rule of thumb, the frequency deviation for th e tru-05 0 vcxo is 300 ppm over the 1 v to 4 v range v c . for example, a 10 mhz vcxo has an average gain of 1000 hz/v. the peak value of kv is about twice this value at approximately 2.5 v, and one half this value at 1 v and 4 v . for many loop calculations, the gain is expressed in rad/vs which would be 2 p (100 ppm * f 0 /vs) for the previous example. v e c t r o n i n t e r n at i on a l 1 6 6 glo v e r a v e n u e , n o r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l: v e ct r o n @ v e c t ro n . c o m 200 150 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 contro l vo l t age (vc) tru-05 0 vcxo frequency deviation vs. control voltage figur e 1 1. v = 5.00 v, 25 c 8.192 mhz dd 7 o f 1 7 how is quality assured? in addition to extensive testing, the basic design consists of a few highly engineered, robust components; quality is further assured by advanced ceramic packaging and fully automated assembl y . o s c i l l a t o r a g i n g any crystal stabilized oscillator typically exhibits a small shift in output frequency during aging. the major factors which lead to this shift are changes in the mechanical stress on the crystal and mass-loading of foreign material on the crystal. as the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the crystal mounting arrangement can lead to frequency variations. vectron has minimized these two effects through the use of a miniature a t -cut strip resonator crystal which allows a superior mounting arrangement and results in minimal relaxation and almost negligible environmental stress transfe r .
a b s o l u t e p u l l r a n g e absolute pull range (apr) is specified by the fourth character of the product code (see figure 26). apr is the minimum guaranteed frequency shift from f 0 over variations in temperature, aging, power supply and load. both frequency and environment limit the specified apr. the total pull range for the vcxo contained in th e tru-050 is typically between 200 ppm and 400 ppm. a 50 ppm ap r tru-05 0 fully tracks a 50 ppm source oscillator or any other 50 ppm reference over the operating temperature range, life of the product, power supply and measurement variations. o u t p u t d i v i d e r c i r c u i t an internal 2 n divided output is available at out2. the value of n varies from 1 to 8 and is set during manufacture. this provides divide ratios from 2 to 256 . a ?o output?option may also be selected to minimize power usage and jitter. divider note : the frequency of out1 is the fundamental frequency of the vcxo used in the tru-050. the lowest frequency vcxo (out1) available in the tru-050 is 12 mhz, and the highest frequency is 65.536 mhz. therefore, the frequency range of out1 is between 12 mhz and 65.536 mhz. since out2 is a division of out1 and can vary from out1 ?2 to out1 ?256, out2 ranges from 46.875 khz (12 mhz ?256) to 32.768 mhz (65.536 mhz ?2). lower frequency inputs may be supplied to the phase detector of the tru- 050, but an external divider in the feedback loop is required. with an external divider in the feedback loop, clock and data signals down to 8 khz can be used as phase detector inputs. v e c t r o n i n t e r n a t i on a l 1 6 6 glo v e r a v e n u e , n o r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l: v ec t r o n @ v e c t ro n . c o m 8 o f 1 7 mass-loading on the crystal generally results in a frequency decrease and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non-hermetic package. vectron has minimized the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number of internal components through the use of asic technolog y . under normal operating conditions with an operating temperature of 40?, th e tru-05 0 will typically exhibit 2 ppm aging in the first year of operation. the device will then exhibit 1 ppm aging the following year with a logarithmic decline each year thereafte r . i m n o t f a mi l ia r wit h a p r . could you explain it in more detail? apr is the guaranteed frequency err or (in ppm) the vcxo can track. this takes the guesswork out of the total pull range which drifts and is affected by temperature, aging, power supply etc. every tru-050 is tested for pull range over the operating temperature range, making it one of the most reliable devices on the market. w h a t s t h e d i f f e re n c e b etw e e n ou t 1 a n d o u t 2? out1 is the direct output from the vcxo and is limited to frequencies in the 12 mhz to 65 mhz range. out2 is an optiona l 2 n divided vcxo output. the divide ratio is factory set at 2, 4, 8, .. . o r 2 n , up to 256.
h a n d l i n g p r e c a u t i o n s although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposu r e to electrostatic discharge (esd) during handling and mounting. vectron employs a human body model (hbm) and a charged device model (cdm) for esd susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the mode. although no industry-wide standard has been adopted for cdm, a standard hbm (resistance = 150 0 w , capacitance = 100 pf) is widely used and therefore can be used for comparison purposes. the hbm esd threshold presented here was obtained using these circuit parameters. v e c t r o n i n t e r n a t i onal 1 66 glover a ve n u e , no r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l: v ec t r o n @ v e c t ro n . c o m mode l esd threshold, minimu m unit human bod y 2000 * v charged devic e 200 0 v t able 3. * mil-std-883d, method 3015, class 1 9 o f 1 7 how is it packaged? the tru-050 is a very robust product which is assembled on an automated manufacturing line. it is packaged in a 16-pin, ceramic dip with a seam-welded step lid, hermetically sealed for long ter m reliability. options include thru-hole and surface mount terminals and an extended tempe r - ature range. tape and reel packaging is also available.
v e c t r on i n t e r na t io n a l 1 6 6 g l o v e r a v e nue , n or w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e- m a i l: v e ct r o n @ v e c t ro n . c o m a typical pll is illustrated in figure 12. be advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are based on ideal systems. such equations may not be accurate for real systems with nonlinearities, dc offsets and noise. a pll is a feedback system which forces the output frequency to lockin both phase and frequency to the fundamental frequency of the input signal. when initially out of lock, the output of the phase detector is proportional to the difference in frequency between the two phase detector inputs. this beat note varies the output frequency of the vcxo, and in a properly designed phase-locked loop, the loop action forces v c to the co r r ect value to bring the system into lock. a designer? primary concern is to select a loop filter that ensures lockin and stability, while providing adequate filtering of input signal noise or jitter. an initial design starts with a known d a t ain signal and an output specification. an initial analysis of the open loop gain response provides insight into the response of the system. using figure 12, the open loop gain is: g(s)= kp kv a v(s) sn where: kp is the phase detector gain in v/rad (-0.53 x data density). kv is the vcxo gain constant in rad/vs. a v(s) is the loop filter transfer function. n is the divide ratio. 1/s converts the vcxo frequency output to a phase output. the open loop gain may be plotted and varied using the spice model provided in figure 13. the gain, frequenc y , and loop filter configurations may be varied to producedesired responses. in the first-order phase-locked loop, where av(s) and n equal 1, the gain curve has a 20 db/decade slope with unity gain at: f = kv k p where kv is in rad/vs. 2 p figure 12. 1 0 o f 1 7 h o w d o e s i t p e r f o r m ?
spice model p p v e c t r o n i n t e r n a t i on a l 1 6 6 glo v e r a v e n u e , no r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l: v ec t r o n @ v e c t ro n . c o m the first-order open loop gain has a constant phase shift of 90 degrees. however, other frequency poles are present in the loop due to the op-amp's limited bandwidth and gain, the phase detector and the vcxo modulation bandwidth (these poles are included in the spice model). the loop's bandwidth is approximately equal to the closed loop bandwidth and can be used to assess the stability, lockin range and filtering characteristics of the loop. the loop acts as a bandpass filter centered at the clock frequency, just as if a tank circuit were used to filter the input clock or data stream. however, the filter q of th e tru-05 0 is much greater than that of a tank circuit and typically ranges from 1,000 to 20,000. the pll tracks input phase jitter inside the loop bandwidth while jitter is attenuated outside the loop bandwidth. converting the spice model (figure 13) to a closed loop illustrates the jitter transfer function shown in figure 15. in general, the pll rapidly locks those signals with an initial frequency difference (relative to clkin) that is within the loop's bandwidth. lockin time is longer for lower bandwidth loops and may be degraded by jitter or by poor input duty cycle. s i m u l a t e d r e s u l t s the spice model just described can be used to determine the component values necessary to produce a desired loop filter bandwidth, its jitter transfer function and its open loop response for a given application. alternatively, simulation results can be obtained using vectron's " tru-05 0 loop filter calculation" software. this software runs from dos and will also provide the user with loop filter component values r1, rf and cf (see figure 15) based on desired loop filter bandwidth, data type, data density, damping factor and data frequency. for assistance with your specific application, or to receive a copy of vectron's " tru-05 0 loop filter calculation" software, please contact vectron s application engineering staff. figure 13. 1 1 of 17
v e c t r o n i n t e r na t i o nal 1 6 6 g l o ver a venue , no r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - m a i l : v e c t r o n @ v e c t ro n . c o m ? s p i c e s i m u l a t e d r e s u l t s figure 14. figure 15. 1 2 of 17
a p p l i c a t i o n s the three key applications for th e tru-05 0 are clock recovery of digital data, frequency translation and clock smoothing. these timing needs are required by a wide variety of markets such as telecommunications, datacommunications, digital video and audio, telemetr y , test equipment and sensing. c l o c k r e c o v e r y a n d d a t a r e t i m i n g th e tru-05 0 was designed to recover a clock imbedded in an nrz data signal, and retime it with a data pattern. in this application, the vcxo frequency is exactly the same as the nrz data rate and the outputs are taken off pi n 1 1 (recovered clock) and pin 12 (recovered data). the diagram below shows a typical circuit. figure 17 shows the relationship between d a t ain (pin 7) and clkin (pin 9) under locked conditions. the rising edge of the clkin is centered to the d a t ain pulse. v e c t r on i n t e r n a t ion a l 1 6 6 g l o v e r a v e n u e , n o r w a l k , c t 06 8 5 6 - 5 16 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - m a i l : v ec t r o n @ v e c t ro n . c o m figure 16. figure 17. 1 3 o f 1 7 is vectron iso r egistered? y es! vectron s quality system was registered to iso 9 0 0 1 i n o c t o b e r 1 9 9 6 . h o w i s i t u s e d ? relationship of rclk (pin 11) and rd a t a (pin 12). the falling edge of the recovered clock is in the middle of the data pattern and should be used to clock the data into the next part of the circuit. there is a one and a half cycle delay (frequency of pin 9) between d a t ain and rd a t a. therefore a 10 mhz signal would have a 150 ns delay between da t ain and rda t a plus additional circuit delays, which are typically 9 ns.
t i m i n g r e c o v e r y u s i n g o u t 2 due to the limitations in crystal size, the lowest frequency from out1 is 12 mhz. for applications below this frequency, the internal divide-by can be used (note: an additional external divide-by can also be used). an application for 1.544 mhz clock recovery is shown in figure 19. v e c t r on i n t e r n a t i o n a l 1 66 g lov e r a venue, n or w a l k , c t 0685 6 - 5 16 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma il: v e c t r o n @ v e c t ro n . c o m figure 18. figure 19. rclk rd a t a 1 4 o f 1 7 f r e q u e n c y t r a n s l a t i o n th e tru-05 0 is most commonly used for frequency translation. for example, in a telecommunications application, when a 2.048 mhz reference clock is multiplied to 32.768 mhz, a very clean 32.768 mhz clock would then be output to other circuits. generally, th e tru-05 0 is specified in terms of nrz input. since th e tru-05 0 s phase detector was designed for nrz data, other inputs such as a clock signa l s h o u l d b e c o n s id e r ed a s a n e qu i v a l e n t 1 01 0. . . n r z p a t t e r n . eye diagram for tru-050 @ 51.84 mhz the falling edge of rclk is centered with respect to rda t a ch . 1 = 1 . 0 0 0 v o l t s / d i v o ff s e t = 9 / 6 . 2 m vo l t s ch . 2 = 1 . 0 0 0 v o l t s / d i v o ff s e t = 9 5 1 . 2 m vo l t s t i m e b a s e = 3 . 0 0 0 n s / d i v d e l a y = 1 6 . 0 0 0 0 n s 1 6 . 0 0 0 n s 3 1 . 0 0 0 0 n s 4 6 . 0 0 0 0 n s
i f t h e d a t ai n i np u t t o th e p h a s e de t ec to r i s a c lo c k s i g na l , th e vcx o , o r t h e di v i d e d v cx o ou t p u t f e d bac k t o c l ki n , m ust b e t w i c e t h e d a t a i n ra t e . i n f ig u r e 2 0 , t h e 2. 04 8 m h z s y s t e m r e f e r e nc e c l oc k c a n b e t r e a t e d a s a 4. 09 6 m hz nr z d a ta s t r e a m w i t h a d a t a d en s i t y o f 1 0 0 % . t h e r e f o r e , t h e fe e db a c k fr e qu en c y i n t h e p l l w o u l d b e 4 . 09 6 m h z ( t h e 3 2. 768 mh z c l o c k f r eq ue nc y d i v i d e d b y 8 ) . v e c t r o n i n t e r n a t i onal 1 6 6 glover a ve n u e , no r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l : v ec t r o n @ v e c t ro n . c o m figure 20. figure 21. figure 22. another example would be to translate 8.000 khz to 51.840 mhz. 1 5 o f 1 7 can i get application assistance? absolutely ! j u s t c a l l 1 - 8 8 - vectro n - 1
for applications where the d a t ain is very low in frequency (roughly <200 khz), clock information may pass through the phase detector because of its finite low pass characteristics. in applications such as this, an additional pole may be necessary in the loop filter to attenuate these ac components prior to the vcxo input (note the capacitor to ground in figure 22). please contact vectron? applications engineering staff for further detail. c l o c k s m o o t h i n g e x a m p l e the third common application of th e tru-05 0 is for the regeneration or ?moothing?of a degraded input clock signal. in this application, th e tru-05 0 accepts a degraded input clock signal and regenerates the signal to square up the rising and falling edges and remove unwanted jitter. the output is then a clean quartz locked representation of the degraded input signal. figure 23 illustrates a common example of a clock signal regeneration application. in this example, a degraded 16.384 mhz clock signal is smoothed using the tru-050 . the 16.384 mhz clock is fed into d a t ain (pin 7). the signal is then regenerated, and a smoothed representation of the signal is available at rda t a (pin 11). it is important to note that the signal fed back from out1 (pin 15) to clkin (pin 9) is twice the frequency of the degraded input signal at d a t ain (pin 7). this is because th e tru-05 0 was originally designed for input nrz data patterns. since an nrz data pattern has one transition per bit, and its associated clock has two transitions per bit, the tru-05 0 phase detector requires twice as many transitions at clkin (pin 9) when compared to d a t ain (pin 7). in the case of an input clock signal, clkin (pin 9) must be twice the frequency of d a t ain (pin 7). for a 16.384 mhz clock smoothing application, a tru-05 0 with a 32.768 mhz out1 should be specified. v e c t r o n i n t e r na t io n al 1 6 6 g l o v e r a v e nue , n o r w a l k , c t 0 6 85 6 - 5 1 6 0 t e l : 1 - 8 8 - v e c t r o n - 1 e- m a i l : v e ct r o n @ v e c t ro n . c o m figure 23. 1 6 o f 1 7
v e c t r on i n t e r n a t ion a l 1 6 6 g l o v e r a v e n u e , n o r w a l k , c t 06 8 5 6 - 5 160 t e l : 1 - 8 8 - v e c t r o n - 1 e - ma i l : v e c t r o n @ v e c t ro n . c o m s u r f a c e m o u n t 12.032 16.777 22.1184 30.720 41.2416 51.840 1.000 4.096 6.480 9.486 12.960 20.6208 32.768 12.288 16.896 22.579 32.000 41.943 65.536 1.024 4.1925 6.912 9.720 14.000 20.9715 12.624 17.920 24.576 32.768 44.736 19.440 1.544 4.224 7.680 10.000 16.000 22.368 13.824 18.432 24.704 33.330 47.457 2.048 5.592 8.000 10.240 16.384 23.7285 16.000 18.936 25.000 34.368 49.152 40.960 3.088 6.016 8.192 11.0592 16.665 24.576 16.128 20.000 25.248 38.880 49.408 3.240 6.144 8.448 12.352 19.440 24.704 16.384 20.480 28.000 40.000 50.000 4.032 6.312 8.960 12.500 20.000 25.920 standard frequencies* (mhz) using out1 * other frequencies available upon request. t able 4. figure 25. figure 24. figure 26. standard frequencies* (mhz) using out2 1 7 o f 1 7 h o w i s i t p a c k a g e d ? t h r u - h o l e h o w i s i t o r d e r e d ? questions? give us a call: 1 - 8 8 - vectro n - 1

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